Damascene interconnect structure having air gaps between metal lines and method for fabricating the same

ABSTRACT

An exemplary damascene interconnect structure includes a substrate ( 20 ), a first dielectric layer ( 21 ) on the substrate, a plurality of trenches ( 27 ) formed in the first dielectric layer, and a plurality of metal lines ( 24 ) filled in the trenches. The first dielectric layer includes multi sub-dielectric layers ( 211, 212, 213 ). Wherein a plurality of air gaps ( 28 ) are maintained between the metal lines and at least one of the sub-dielectric layers. A method for fabricating the damascene interconnect structure is also provided.

FIELD OF THE INVENTION

The present invention relates to damascene interconnect structures andmethods for fabricating the same, and particularly to a damasceneinterconnect structure having air gaps between metal lines and a methodfor fabricating the same.

BACKGROUND

In semiconductor devices, such as large scale integrated circuits (LSI)and ultra-large scale integration (ULSI) integrated circuits, thedamascene process has been commonly used to form interconnect lines. Atypical damascene process involves etching trenches or canals in aplanar dielectric layer, and then filling the trenches or canals withmetal, such as aluminum or copper. After filling, the excess metaloutside the trenches is planarized and polished by chemical polishing sothat metal is only left within the trenches.

FIG. 8 is a cross-sectional view of a typical damascene interconnectstructure. The damascene interconnect structure 1 includes a substrate10, a dielectric layer 11 formed on the substrate 10, a plurality oftrenches 15 formed in the dielectric layer 11, a plurality of metallines 17 filled in the trenches 15, and a capping layer 19 covering thedielectric layer 11 and the metal lines 17.

A method for fabricating the damascene interconnect structure is asfollows. In step 1, referring to FIG. 9, a substrate 10 is provided, anda dielectric film 110 and a photoresist layer (not shown) aresequentially formed on the substrate 10. Then, the photoresist layer isformed into a patterned photoresist layer 13 by an exposure anddeveloping process.

In step 2, referring to FIG. 10, by using the patterned photoresistlayer 13 as a mask, the dielectric film 110 is etched to form aplurality of trenches 15. Thereby, remaining portions of the dielectricfilm 110 define a dielectric layer 11.

In step 3, referring to FIG. 11, a metal layer 170 is deposited on thedielectric layer 11 and is completely filled in the trenches 15.

In step 4, referring to FIG. 12, the metal layer 170 is polished with achemical mechanical polishing (CMP) process. Thereby, excess portions ofthe metal layer 170 covering the dielectric wall 11 are removed, andonly portions of the metal in the trenches 15 remain. These remainingportions form a plurality of metal lines 17. Then a capping layer 19 isdeposited on the dielectric layer 11 and the metal lines 17, so as toform the damascene interconnect structure 1.

In order that the damascene interconnect structure 1 has good electricalproperties, a resistance R in the metal lines 17 and a capacitance Cbetween the metal lines 17 must both be as low as possible. This is sothat the resistance-capacitance (RC) delay and leakage current caused bythe resistance R and the capacitance C can be minimal.

With recent developments in semiconductor technology, millions and evenbillions of electronic elements can be integrated in one chip. Currentflows and electrical processing occurring in a single chip are massive.Therefore leakage current and RC delay can be prevalent, and maysignificantly impair the performance of the chip.

What is needed is a damascene interconnect structure and a method forfabricating the same which can help ensure that performance of acorresponding integrated circuit is satisfactory.

SUMMARY

An exemplary damascene interconnect structure includes a substrate, afirst dielectric layer on the substrate, a plurality of trenches formedin the first dielectric layer, and a plurality of metal lines filled inthe trenches. The first dielectric layer includes multi sub-dielectriclayers. Wherein a plurality of air gaps are maintained between the metallines and at least one of the sub-dielectric layers.

An exemplary method for fabricating a damascene interconnect structureis provided as below. A substrate is provided. A multilayer dielectricfilm is formed on the substrate. A patterned photoresist is formed onthe multilayer dielectric film. Etching the multilayer dielectric filmto form a plurality of trenches, a portion of each of the trencheshaving an enlarged width at each of sidewalls thereof. Filling thetrenches with conductive metal to form conductive lines such that air istrapped in extremities of the enlarged width portions of the trenches.

Other novel features and advantages will become more apparent from thefollowing detailed description when taken in conjunction with theaccompanying drawings. In the drawings, all the views are schematic.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a side cross-sectional view of a damascene interconnectstructure according to a preferred embodiment of the present invention.

FIG. 2 to FIG. 7 are schematic, cross-sectional views of sequentialstages in an exemplary method for fabricating the damascene interconnectstructure of FIG. 1.

FIG. 8 is a side cross-sectional view of a conventional damasceneinterconnect structure.

FIG. 9 to FIG. 12 are schematic, cross-sectional views of sequentialstages in a method for fabricating the damascene interconnect structureof FIG. 8.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 is a side cross-sectional view of a damascene interconnectstructure according to a preferred embodiment of the present invention.The damascene interconnect structure 2 includes a substrate 20, a firstdielectric layer 21 on the substrate 20, a plurality of trenches 27 inthe first dielectric layer 21, a plurality of metal lines 24 in thetrenches 27, a capping layer 25 functioning as a diffusion barriercovering the first dielectric layer 21 and the metal lines 24, and asecond dielectric layer 26 on the capping layer 25 for insulating themetal lines 24 from other electrical elements.

The first dielectric layer 21 is a multilayer structure, which includesa first sub-dielectric layer 211, a second sub-dielectric layer 212, anda third sub-dielectric layer 213 arranged in that order from bottom totop. The first and the third sub-dielectric layers 211 and 213 reachside edges of the metal lines 24. The second sub-dielectric layer 212maintains a distance from the metal lines 24, so that a plurality of airgaps 28 are maintained between the metal lines 24 and the secondsub-dielectric layer 212.

The first dielectric layer 21 is a multilayer structure with a pluralityof air gaps 28 between the metal lines 24 and the second sub-dielectriclayer 212. Because each air gap 28 has the lowest dielectric constant(k=1), the capacitance C between adjacent metal lines 24 issignificantly reduced. Accordingly, RC delay of electrical signals andleakage current are reduced. Therefore the speed of an integratedcircuit incorporating the damascene interconnect structure 2 issignificantly improved, and power consumption of the integrated circuitis reduced.

An exemplary method for fabricating the damascene interconnect structure2 is as follows. In step 11, referring to FIG. 2, a substrate 20 isprovided, and then a first, a second, and a third dielectric films 201,202 and 203 are sequentially formed on the substrate 20. The first andthe third dielectric films 201 and 203 can be silicon nitride (SiN_(x))films, and the second dielectric film 202 can be a silicon oxide(SiO_(x)) film.

In step 12, referring to FIG. 3, a photoresist layer (not shown) isformed on the third dielectric film 203. Then the photoresist layer isexposed and developed to form a patterned photoresist layer 22.

In step 13, referring to FIG. 4, the three dielectric films 201, 202,203 are etched to form a plurality of trenches 27 by means of a wetetching method. An etchant of the wet etching method is a mixture ofhydrogen fluoride (HF) and ammonium fluoride (NH₄F). Because siliconoxide has a faster etching rate than that of silicon nitride in theetchant, the second dielectric film 202 at the trenches 27 is etchedwider than the first and the third dielectric films 201 and 203. Thus, aportion of each of the trenches 27 has an enlarged width (not labeled)at each sidewall thereof. The remaining parts of the first, the second,and the third dielectric films 201, 202 and 203 constitute first,second, and third sub-dielectric layers 211, 212 and 213, respectively.The three sub-dielectric layers 211, 212 and 213 cooperatively form afirst dielectric layer 21.

In step 14, referring to FIG. 5, the patterned photoresist layer 22 isremoved. Then a metal layer 240 is deposited on the first dielectriclayer 21 so that the metal layer 240 also fills into the trenches 27.This can be performed by physical vapor deposition (PVD). The metallayer 240 can be made of copper. During the PVD process, the PVD intothe trenches 27 is substantially collimated. Therefore the first and thethird sub-dielectric layers 211 and 213 at the trenches 27 act asbarriers, and the copper atoms being deposited cannot enter theextremities of the enlarged width portions of the trenches 27. Thus airis trapped in the enlarged width portions of the trenches 27, therebyforming the air gaps 28.

In step 15, referring to FIG. 6, the metal layer 240 is polished with aCMP process in order to remove excess portions of the metal layer 240over the third sub-dielectric layer 213. Thereby, the portions of themetal layer 240 remaining within the trenches 27 constitutes a pluralityof metal lines 24.

In step 16, referring to FIG. 7, a capping layer 25 is deposited on themetal lines 24 and the third sub-dielectric layer 213. Then a seconddielectric layer 26 is deposited on the capping layer 25, so as to forma damascene interconnect structure 2.

In the above-described method for fabricating the damascene interconnectstructure 2, the first dielectric layer 21 is formed by depositing threesub-dielectric layers 211, 212, 213 with different materials, and byetching the first dielectric layer 21 to form the trenches 27 having theenlarged width portions at the sidewalls thereof. Therefore when themetal lines 24 are formed in the trenches 27, air gaps 28 are alsoformed in the extremities of the enlarged width portions of the trenches27. Because the air gaps 28 have the lowest dielectric constant of air,a capacitance C between adjacent metal lines 24 can be significantlyreduced. Thus in a corresponding integrated circuit chip, RC delay inelectrical signals and leakage current are reduced. Accordingly, thespeed and power consumption characteristics of the integrated circuitchip can be significantly improved.

Various alternative embodiments can be practiced. For example, thefirst, the second, and the third sub-dielectric layers 211, 212, 213 canbe made of the same material. Such material can be silicon oxide orsilicon nitride. During the deposition process, a deposition rate of thesecond sub-dielectric layer 212 is lower than that of the firstsub-dielectric layer 211, and a deposition rate of the thirdsub-dielectric layer 213 is higher than that of the secondsub-dielectric layer 212. Therefore the densities of the first and thethird sub-dielectric layers 211 and 213 are greater than that of thesecond sub-dielectric layer 212. Accordingly, etching rates of the firstand the third sub-dielectric layers 211 and 213 are lower than that ofthe second sub-dielectric layer 212. During the etching process,portions of the trenches 27 at the second sub-dielectric layer 212 arewider than portions of the trenches 27 at the first and the thirdsub-dielectric layer 211, 213. As a result, air gaps 28 are subsequentlyformed between the metal lines 24.

The metal lines 24 can be made of another suitable material, such asaluminum, silver, or an alloy including any one or more of copper,aluminum and silver.

The first dielectric layer 21 can be a multilayer structure having two,four or more sub-dielectric layers, so long as air gaps 28 aremaintained between the metal lines 24 and at least one of thesub-dielectric layers.

The trenches 27 can be etched by dry etching method. In such method, theetchant can be a mixture of sulfur hexafluoride (SF₆) gas and carbontetrafluoride (CF₄) gas.

It is to be further understood that even though numerous characteristicsand advantages of the present embodiments have been set out in theforegoing description, together with details of the structures andfunctions of the embodiments, the disclosure is illustrative only, andchanges may be made in detail, especially in matters of shape, size, andarrangement of parts within the principles of the invention to the fullextent indicated by the broad general meaning of the terms in which theappended claims are expressed.

1. A damascene interconnect structure, comprising: a substrate; a firstdielectric layer on the substrate, the first dielectric layer comprisinga plurality of sub-dielectric layers; a plurality of trenches formed inthe first dielectric layer; and a plurality of metal lines filled in thetrenches; wherein a plurality of air gaps are maintained between themetal lines and at least one of the sub-dielectric layers.
 2. Thedamascene interconnect structure as claimed in claim 1, wherein theplurality of sub-dielectric layers comprises a first, a second, and athird sub-dielectric layers arranged in that order from bottom to top,and the air gaps are maintained between the metal lines and the secondsub-dielectric layer.
 3. The damascene interconnect structure as claimedin claim 2, wherein the first and the third sub-dielectric layers aresilicon nitride layers, and the second sub-dielectric layer is a siliconoxide layer.
 4. The damascene interconnect structure as claimed in claim2, wherein the first, the second, and the third sub-dielectric layersare silicon nitride layers, and a density of each of the first and thethird sub-dielectric layers is greater than that of the secondsub-dielectric layer.
 5. The damascene interconnect structure as claimedin claim 2, wherein the first, the second, and the third sub-dielectriclayers are silicon oxide layers, and a density of each of the first andthe third sub-dielectric layers is greater than that of the secondsub-dielectric layer.
 6. The damascene interconnect structure as claimedin claim 1, further comprising a capping layer and a second dielectriclayer, the capping layer covering the first dielectric layer and themetal lines, and the second dielectric layer covering the capping layer.7. The damascene interconnect structure as claimed in claim 2, whereinmaterial of the metal lines is at least one of copper, silver, aluminum,and an alloy comprising any one or more of copper, aluminum and silver.8. A method for fabricating a damascene interconnect structure, themethod comprising: providing a substrate; depositing a multilayerdielectric film on the substrate; forming a patterned photoresist on themultilayer dielectric film; etching the multilayer dielectric film toform a plurality of trenches, a portion of each of the trenches havingan enlarged width at each of sidewalls thereof; filling the trencheswith conductive metal to form conductive lines such that air is trappedin extremities of the enlarged width portions of the trenches.
 9. Themethod for fabricating a damascene interconnect structure as claimed inclaim 8, wherein the conductive metal filled in the trenches is formedby means of physical vapor deposition.
 10. The method for fabricating adamascene interconnect structure as claimed in claim 8, wherein themultilayer dielectric film comprises a first, a second, and a thirdsub-dielectric layer, and the air is trapped between the secondsub-dielectric layer and the conductive lines.
 11. The method forfabricating a damascene interconnect structure as claimed in claim 10,wherein the first and the third sub-dielectric layer are silicon nitridelayers, and the second sub-dielectric layer is a silicon oxide layer.12. The method for fabricating a damascene interconnect structure asclaimed in claim 10, wherein all three sub-dielectric layers are siliconnitride layers or silicon oxide layers, and a deposition rate of each ofthe first and the third sub-dielectric layers is greater than that ofthe second sub-dielectric layer.
 13. The method for fabricating adamascene interconnect structure as claimed in claim 8, wherein themultilayer dielectric layer is etched by a wet etching method.
 14. Themethod for fabricating a damascene interconnect structure as claimed inclaim 13, wherein an etchant of the wet etching method is a mixture ofhydrogen fluoride and ammonium fluoride.
 15. The method for fabricatinga damascene interconnect structure as claimed in claim 8, wherein themultilayer dielectric layer is etched by a dry etching method.
 16. Themethod for fabricating a damascene interconnect structure as claimed inclaim 15, wherein an etchant of the dry etching method is a mixture ofsulfur hexafluoride and carbon tetrafluoride.
 17. The method forfabricating a damascene interconnect structure as claimed in claim 8,further comprising forming a capping layer covering the multilayerdielectric layer and the conductive lines, and forming a dielectriclayer on the capping layer.
 18. The method for fabricating a damasceneinterconnect structure as claimed in claim 8, wherein material of theconductive lines is at least one of copper, aluminum, silver, and analloy comprising any one or more of copper, aluminum and silver.